Class Notes:

The Class was given a PowerPoint Presentation on Nanologic and majority logic synthesis.  The presentation was divided into two lectures. In the first lecture they were told on different types of future Nano devices and the logic associated with them.  Then we introduced a K-map based logic synthesis method to transform common logic circuits designed in Boolean logic (AND/OR logic) into equivalent majority gate logic.

(Download Power Point Presentation)

Data Sheets:

1. Worksheet 1

Students were asked to fill out and submit the worksheets at the end of the first lecture. It deals with how the flow of information takes place in QCA majority gate architecture. (Download Worksheet 1)

2. Worksheet 2

 Students were asked to fill out and submit the worksheets at the end of the first lecture. It deals with how a 3-input majority gate can be represented as an AND or OR gate by fixing one of its inputs as a 0 or 1 respectively. (Download Worksheet 2)

3. Worksheet 3

 Students were asked to fill out and submit the worksheets at the end of the second lecture. It deals with how a K-map based synthesis method is used to represent a logic expression in majority gate based logic.(Download Worksheet 3)

4. Student Survey

 A survey was conducted at the end of the Knowledge module. Students were asked to answer seven questions in order to determine the effect of this knowledge module on student learning. Here are five the sample surveys that we collected.(Download Student Survey)

Sample Survey:

Survey 1

Survey 2

Survey 3

Survey 4

Survey 5

Sample Worksheet 1:

Sample Worksheet 2:

Sample Worksheet 3: